The present invention relates to a method of designing a semiconductor integrated circuit, a designing apparatus, and an inspection apparatus, particularly to a method of designing a semiconductor integrated circuit and a designing apparatus for designing a high-speed operation circuit in which stability of the whole semiconductor integrated circuit is secured and an increase of a leak current is suppressed, and an inspection apparatus for a semiconductor integrated circuit, which reduces a leak current to thereby stably operate.
In recent years, with speeding-up/reduction of threshold values of the semiconductor integrated circuit, power consumption of the circuit has increased more than ever. The power consumption also includes the leak current, and as a method of reducing the leak current, a designing method is well known in which the circuit is designed in such a manner as to arrange transistors having high and low threshold values in a mixed manner. In this designing method, a high-speed transistor having a small threshold value (i.e., the leak current is large) is used in a portion in which high speed is required, and a low-speed transistor having a large threshold value (i.e., the leak current is small) is used in another portion. Accordingly, while the leak current of the whole circuit is kept to be small, the speed is raised.
However, when this replacement is performed, the following problem occurs. As shown in 13(a), when 1 is input into both inputs of a circuit (NAND circuit in this drawing) including PMOSs arranged in parallel, output indicates a value floating a little from a value of 0 (the value does not completely agree with a predetermined value, and has a difference from the predetermined value) because of the leak current on a PMOS side. For example, the output is 0.05 V with respect to a power voltage of 1 V.
Furthermore, as shown in FIG. 14, in a circuit in which the number of transistors arranged in parallel increases, and three inputs are arranged in parallel (3-input NAND circuit in this example), a voltage further distant from a ground voltage is output. This phenomenon remarkably appears in a transistor having a small threshold value as shown in FIGS. 13(a) (b). When the transistor having a large threshold value is used as shown in FIGS. 12(a) (b), the leak current of the transistor itself is small, and therefore a problem is small.
Moreover, when a floating output (e.g., 0.95 V) is received by a PMOS juxtaposed circuit (e.g., the NAND circuit) as shown in FIGS. 15(a) (b), the output further floats. Therefore, for example, in the example shown in FIG. 15(b), 0.10 V is output, and the leak current of the transistor which receives the output voltage indicates a large value. When an input voltage floats from a power voltage or ground voltage as shown in FIGS. 15(b) and 16(b), a potential difference is generated between gate and source of the transistor which receives the input, and the leak current exponentially increases because of properties of the transistor (see FIG. 17). Therefore, problems occur that the leak current of the whole circuit increases, or a circuit operation becomes unstable. This phenomenon does not raise a very large problem with respect to an output on a 1-side of a juxtaposed portion in a PMOS circuit, or an output on a 0-side of a juxtaposed portion in a NMOS circuit as shown in FIGS. 15(a) and 16(a). This is because the voltage floats a little.
It is to be noted that a circuit shown in FIGS. 18(a) (b) is a constitution example in which AND-NOR circuits are continuously arranged. FIG. 18(a) is a transistor connection diagram, and FIG. 18(b) is a logical circuit diagram. In a logical circuit constitution, an AND circuit for calculating a logical product of inputs B and C, and a NOR circuit for calculating exclusive OR of two inputs including the output of the AND circuit as input A are continuously arranged as shown in FIG. 18(b). In the transistor circuit shown in FIG. 18(a), a logical operation in a case where inputs A, B, C are changed at 0 V and 1 V is shown in FIGS. 19(a) (b).
FIG. 19(a) shows a case where the input A is 0 V, and inputs B, C are 1 V, and a leak current is generated in a juxtaposed PMOS transistor disposed in an upper stage. FIG. 19(b) shows a case where inputs A, B are 0 V, and input C is 1 V, and a leak current is generated in a juxtaposed NMOS transistor disposed in a lower stage. A deviation between an operation voltage and a power voltage of a portion in which leak occurs is caused. When the high-speed transistor having a small threshold value is applied to this portion, a problem occurs.
It is to be noted that as prior techniques of the present application, there are U.S. Pat. No. 6,380,761B1, Japanese Patent Application Laid-open No. 2002-9242 and the like.
As described above, in the conventional semiconductor integrated circuit design, the transistor constituting the logical circuit in order to speed up the circuit operation is uniformly replaced with the high-speed transistor having the small threshold value. Then, the leak current increases in a case where the logical circuits having juxtaposed inputs are continuously arranged. There are problems that the deviation between the operation voltage and the power voltage or the ground voltage increases, and the operation of the logical circuit becomes unstable because of the deviation generated between the operation voltage and the power voltage.
Therefore, in order to prevent a signal from being separated from the power voltage and the ground voltage, there has been a demand for a semiconductor integrated circuit capable of preventing the signal from being separated from the power voltage and the ground voltage, or preventing the separation from being propagated to a subsequent stage, or further capable of securing circuit operation stability, and preventing increase of the leak current of the transistor by replacement with a transistor having a large threshold value or replacement/insertion with a circuit having a small number of juxtaposed transistors.